A typical ECL gate 10, illustrated in FIG. 1, includes a pair of gate transistors Q1 and Q2 forming an input transistor Q1 and a reference transistor Q2 with common emitter coupling at node 12. The gate transistors Q1 and Q2 provide alternative current paths through respective collector resistors or swing voltage resistors R1 and R2 from high potential V.sub.cc. An ECL current source transistor Q3 is coupled between the common emitter coupling node 12 and low potential V.sub.EE through current source resistor or tail resistor R3. In this example, the ECL gate resistances R1, R2 and R3 are equal. Current source Q3 generates gate current in the alternative current paths according to the input signal V.sub.IN at the base of input transistor Q1. A bias voltage generator also known as a current source voltage generator or reference voltage generator not shown provides the reference voltage V.sub.BB applied at the base of reference transistor Q2 and the current source voltage V.sub.cs applied at the base of the current source transistor Q3. Typical ECL gates also include the differential signal input configuration in which the gate transistors constitute differential input transistors for differential inputs V.sub.IN and V.sub.IN instead of an input transistor and reference transistor having inputs V.sub.IN and V.sub.BB.
ECL circuits generally operate in the negative voltage range with the high potential level V.sub.cc for example at ground potential and low potential V.sub.EE for example at -5.0 volts. Alternatively if V.sub.cc is set at +5.0 volts then low potential V.sub.EE may be set at ground potential. In the negative voltage range the reference voltage level V.sub.BB is referenced to high potential V.sub.cc and set for example in the range of -1.2 to -2.0 volts. The logic high and low level voltage signals are set on either side of the reference voltage. For example with a reference voltage of -1.2 volts the signal voltage swings between a high level voltage signal in the range of for example -0.8 volts and a low level voltage signal in the range of for example -1.6 volts. For a reference voltage V.sub.BB of for example -2.0 volts the signal voltage may swing between for example -1.6 volts and -2.4 volts.
The current source transistor Q3 is base driven by the current source voltage V.sub.cs derived from the separate bias voltage generator or current source voltage generator, not shown. The current source voltage V.sub.cs may have a variety of different temperature characteristics according to the type of generator used. The current source transistor Q3 in cooperation with the current source voltage generator generates the ECL gate current or tail current through current source resistor R3. The gate current passes through either of the alternative transistor collector paths, that is, through resistor R1 or resistor R2, according to the high or low level voltage input signal V.sub.IN applied to the base of input transistor Q1. Complementary ECL gate output signals may be taken from the collectors respectively of input transistor Q1 and reference transistor Q2 and the output signal voltage swing is set by the swing resistors R1 and R2 and the gate current.
On a typical bipolar process integrated circuit chip the ECL gate resistors are formed from doped silicon and have a positive temperature coefficient. Therefore as the temperature increases so does the value of the respective resistances, decreasing the gate current. If V.sub.cs is made to vary so that the gate current is constant, the signal voltage swing will increase significantly with higher temperature due to the positive temperature coefficient of the silicon resistors. This increase in the swing voltage results in slow down of the ECL gate at higher temperatures. Slow down of the ECL gate may also occur at low temperatures because the resistance of silicon base resistors at typical doping levels also increases as temperature falls below room temperature.
In order to maintain a relatively constant signal swing voltage, V.sub.cs must vary negatively with increasing temperature in the same manner as the base emitter voltage drop V.sub.BE varies. The objective is to stabilize the tail voltage V'. According to this prior art arrangement the gate current decreases with increasing temperature. As noted above, this reduction in gate current tends to slow down the operation of the ECL gate.
According to one prior art approach using silicon base resistor technology, temperature compensation is provided by adjusting the temperature coefficient of the voltage generator output. This compensation can be arranged to achieve either a constant gate current I.sub.tail or constant signal voltage swing but not both. However, undesirable parasitic capacitance is introduced. The typical silicon resistor consists of a portion of the epitaxial silicon layer doped for example with P-type silicon during the base implant step. This silicon resistor, referred to as the base resistor, overlies the N-type silicon buried layer. The N-type silicon buried layer in turn overlies the P-type silicon substrate of the integrated circuit die. The silicon resistor is therefore capacitively coupled to the substrate through two PN junction capacitors. This parasitic capacitance results in high power dissipation by the compensated ECL gate.
A secondary effect is also associated with conventional temperature compensating methods using base resistors. While the base resistors of P-type silicon start out with high capacitance, this capacitive coupling to the substrate increases with temperature slowing down the operation of the gate even more.
According to prior art polysilicon resistor technology, the same method adjustment of the voltage generator output is also subject to limitations. The prior art polyresistor network can provide only constant gate current or constant voltage swing but not both.
An attempt was made by the present inventors to substitute low capacitance and low capacitive coupling resistor structures for the prior art ECL gate silicon resistances in temperature compensated silicon resistor networks, using resistor materials with negative temperature coefficient. For example polysilicon resistors used in polysilicon bipolar fabrication processes have much lower parasitic capacitance for higher speed operation of the ECL gate. However the temperature characteristic or coefficient of polysilicon resistor structures is negative. As temperature increases the resistance decreases and the gate current increases. This may lead to even higher temperatures, lower resistances and higher gate current. The positive feedback divergence may lead to "thermal runaway." Even if the IC package is constructed with adequate heat dissipation to control thermal runaway, power dissipation nevertheless increases at high temperatures and high junction temperatures effect the reliability of the device.